ICS412 - Fall 2009 - Homework #1 -

Work alone
You are expected to do your own work on all homework assignments. You may (and are encouraged to) engage in general discussions with your classmates regarding the assignments, but specific details of a solution, including the solution itself, must always be your own work. (See the statement of Academic Dishonesty on the course's syllabus.)

What to turn in?
You can turn your answers on paper on the day the assignment is due (during class or in my office). Alternately you can turn in an electronic copy via e-mail to henric@hawaii.edu and to altunkay@hawaii.edu with a subject line like "ICS412: HW#1" before 11:59PM on the day the assignment is due.

Exercise #1: Textbook 1.8 [8pts]
Which of the following instructions should be privileged?
  1. Set value of timer.
  2. Read the clock.
  3. Clear memory.
  4. Issue a trap instruction.
  5. Turn off interrupts.
  6. Modify entries in device-status table.
  7. Switch from user to kernel mode.
  8. Access I/O device.

Exercise #2: Textbook 1.23 [6pts]
Direct Memory Access is used for high-speed I/O devices in order to avoid increasing the CPU's execution load.

  1. How does the CPU interface with the device to coordinate the transfer?
  2. How does the CPU know when the memory operations are complete?
  3. The CPU is allowed to execute other programs while the DMA controller is transferring data. Does this process interfere with the execution of the user programs? If so, describe what form of interference are caused.

Exercise #3: [5pts]
Why are caches useful? What problem do they solve? What problems do they cause? If a cache can be made as large as the device for which it is caching (for instance, a cache as large as a disk), why not make it that large and eliminate the device?

henric@hawaii.edu